Power Reduction in Pipelines

| The reduction of power consumption for a system level pipeline is addressed in this paper. The pipeline is composed of several stages. Each stage has several behaviours. Di erent behaviours have di ering execution times. The speed of the pipeline is only a ected by the behaviours on the critical path of the slowest stages. Other behaviours can be slowed down to decrease the power consumed in the system. We propose a multi{voltage supply scheme, in which differing behaviours are supplied with di ering voltages. The formulas for computing the supply voltage of each behaviour and minimal power consumption are derived in this paper. The results of computer experiment show that up to 80% hardware power can be saved with this scheme.